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ck409-compliant clock synthesize r CY28405 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07512 rev. *b revised june 16, 2004 features ? supports intel ? springdale/prescott (ck409) ? selectable cpu frequencies ? 3.3v power supply ? nine copies of pci clock ? four copies 3v66 clock with one optional vch ? two copies 48-mhz usb clock ? two copies ref clock ? three differential cpu clock pairs ? dial-a-frequency ? ? supports smbus/i 2 c byte, word, and block read/write ? ideal lexmark spread spectrum profile for maximum electromagnetic interference (emi) reduction ? 48-pin ssop package cpu 3v66 pci ref 48m x 3 x 4 x 9 x 2 x 2 block diagram pin configuration ~ vdd_ref xtal pll ref freq xout xin vdd_pci osc sclk pll 1 wd timer vdd_48mhz sdata vdd_3v66 divider network vdd_cpu fs_[a:e] pd# ref[0:1] vtt_pwrgd# iref 3v66_[0:2] pcif[0:2] pci[0:5] dot_48 3v66_3/vch 2 pll2 cput[0:1,itp], cpuc[0:1,itp] usb_48 i 2 c logic reset# selvch mode ssop-48 **fs_a/ref_0 **fs_b/ref_1 xin xout vss_ref *fs_c/pcif0 *fs_d/pcif1 *fs_e/pcif2 vdd_pci vss_pci pci0 pci1 pci2 pci3 vdd_pci vss_pci pci4 pci5 reset#/pd# dot_48 usb_48 vss_48 vdd_48 vdda vssa vdd dnc*** dnc*** vss cput0 cpuc0 vdd_cpu cput1 cpuc1 vss_cpu cput_itp cpuc_itp sclk sdata 3v66_0 vtt_pwrgd# iref vdd_3v66 3v66_2/mode* 3v66_3/vch/selvch** 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY28405 vdd_ref 3v66_1 vss_3v66 ** 150k internal pull-down * 150k internal pull-up *** do not connect
CY28405 document #: 38-07512 rev. *b page 2 of 19 pin description pin no. name type description 1, 2 ref(0:1) o, se reference clock . 3.3v 14.318-mhz clock output. 1, 2, 7, 8, 9 fs_a, fs_b, fs_c, fs_d, fs_e i 3.3v lvttl latched input for cpu frequency selection . 4xin i crystal connection or external reference frequency input . this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. 5xout o, se crystal connection . connection for an external 14.318-mhz crystal output. 39, 42, 45 cput(0:1,itp) o, dif cpu clock output. differential cpu clock outputs. 38, 41, 44 cpuc(0:1,itp) o, dif cpu clock output . differential cpu clock outputs. 36, 35 dnc do not connect. 30, 29 3v66(0:1) o, se 66-mhz clock output. 3.3v 66-mhz clock from internal vco. 25 3v66_3/vch/selvch i/o, se pd 48- or 66-mhz clock output . 3.3v selectable through external selvch strapping resistor and smbus to be 66 -mhz or 48-mhz. default is 66-mhz. 0 = 66 mhz, 1 = 48 mhz 26 3v66_2/mode i/o, se pu 66-mhz clock output . 3.3v 66-mhz clock from internal vco. reset or power-down mode select. selects between reset# output or pwrdwn# input for the pwrdwn#/reset# pin. default is reset#. 0 = pd#, 1 = reset 7, 8, 9 pcif(0:2) o, se free running pci output . 33-mhz clocks divid ed down from 3v66. 12, 13, 14, 15, 18, 19 pci(0:5) o, se pci clock output . 33-mhz clocks divided down from 3v66. 22 usb_48 o, se fixed 48-mhz clock output . 21 dot_48 o, se fixed 48-mhz clock output . 46 iref i current reference . a precision resistor is attached to this pin which is connected to the internal current reference. 20 reset#/pd# i/o, pu 3.3v lvttl input for power-down# active low . watchdog timeout reset output 33 vtt_pwrgd# i 3.3v lvttl input is a level sensitive strobe used to latch the fs[a:e] input (active low) . 32 sdata i/o smbus compatible sdata . 31 sclk i smbus compatible sclock . 48 vdda pwr 3.3v power supply for pll . 47 vssa gnd ground for pll . 3, 10, 16, 24, 27, 34, 40 vdd(ref,pci,48,3v66,c pu,itp) pwr 3.3v power supply for outputs . 6, 11, 17, 23, 28, 37, 43 vss(ref,pci,48,3v66, cpu,itp) gnd ground for outputs .
CY28405 document #: 38-07512 rev. *b page 3 of 19 mode select the hardware strapping mode input pin can be used to select the functionality of the reset#/pd# pin. the default (internal pull up) configuration is for th is pin to function as a reset# watchdog output. when pulled low during device power-up, the reset#/pd# pin will be config ured to function as a power down input pin. frequency select pins host clock frequency selection is achieved by applying the appropriate logic levels to fs_a through fs_e inputs prior to vtt_pwrgd# assertion (as seen by the clock synthesizer). upon vtt_pwrgd# being sampled low by the clock chip (indicating processor vtt voltage is stable), the clock chip samples the fs_a through fs_e input values. for all logic levels of fs_a through fs_e, vtt_pwrgd# employs a one-shot functionality in that once a valid low on vtt_pwrgd# has been sampled, all further vtt_pwrgd# and fs_a through fs_e transitions will be ignored. table 1. frequency selection table input conditions output frequency vco freq. pll gear constants (g) fs_e fs_d fs_c fs_b fs_a cpu 3v66 pci fsel_4 fsel_3 fsel_2 fsel_1 fsel_0 0 0 0 0 0 100.7 67.1 33.6 805.6 24004009.32 0 0 0 0 1 100.2 66.8 33.4 801.6 24004009.32 0 0 0 1 0 108.0 72.0 36.0 864.0 24004009.32 0 0 0 1 1 101.2 67.5 33.7 809.6 24004009.32 0 0 1 0 0 reserved reserved reserved reserved reserved 0 0 1 0 1 reserved reserved reserved reserved reserved 0 0 1 1 0 reserved reserved reserved reserved reserved 0 0 1 1 1 reserved reserved reserved reserved reserved 0 1 0 0 0 125.7 62.9 31.4 754.2 32005345.76 0 1 0 0 1 130.3 65.1 32.6 781.6 32005345.76 0 1 0 1 0 133.6 66.8 33.4 801.6 32005345.76 0 1 0 1 1 134.2 67.1 33.6 805.2 32005345.76 0 1 1 0 0 134.5 67.3 33.6 807.0 32005345.76 0 1 1 0 1 148.0 74.0 37.0 888.0 32005345.76 0 1 1 1 0 reserved reserved reserved reserved reserved 0 1 1 1 1 reserved reserved reserved reserved reserved 1 0 0 0 0 reserved reserved reserved reserved reserved 1 0 0 0 1 reserved reserved reserved reserved reserved 1 0 0 1 0 167.4 55.8 27.9 669.6 48008018.65 1 0 0 1 1 170.0 56.7 28.3 680.0 48008018.65 1 0 1 0 0 175.0 58.3 29.2 700.0 48008018.65 1 0 1 0 1 180.0 60.0 30.0 720.0 48008018.65 1 0 1 1 0 185.0 61.7 30.8 740.0 48008018.65 1 0 1 1 1 190.0 63.3 31.7 760.0 48008018.65 1 1 0 0 0 100.9 67.3 33.6 807.2 24004009.32 1 1 0 0 1 133.9 67.0 33.5 803.4 32005345.76 1 1 0 1 0 200.9 67.0 33.5 803.6 48008018.65 1 1 0 1 1 reserved reserved reserved reserved reserved 1 1 1 0 0 100.0 66.7 33.3 800.0 24004009.32 1 1 1 0 1 133.3 66.7 33.3 800.0 32005345.76 1 1 1 1 0 200.0 66.7 33.3 800.0 48008018.65 1 1 1 1 1 reserved reserved reserved reserved reserved
CY28405 document #: 38-07512 rev. *b page 4 of 19 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default setting upon power-up, and therefore use of this interface is optional. the interface can also be accessed during power-down operation. data protocol the clock driver serial protocol accepts byte write, byte read, block write and block read operation from any external i 2 c controller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individual indexed bytes. the offset of t he indexed byte is encoded in the command code, as described in table 2 . the block write and block read protocol is outlined in table 3 while table 4 outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 2. command code definition bit description 7 0 = block read or block write operation 1 = byte read or byte write operation (6:0) byte offset for byte read or by te write operation. for block read or block write operations, these bits should be ?0000000? table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8-bit ?00000000? stands for block operation 11:18 command code ? 8-bit ?00000000? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte n/slave acknowledge... 39:46 data byte from slave ? 8 bits .... data byte n ? 8 bits 47 acknowledge .... acknowledge from slave 48:55 data byte from slave ? 8 bits .... stop 56 acknowledge .... data bytes from slave/acknowledge .... data byte n from slave ? 8 bits .... not acknowledge .... stop
CY28405 document #: 38-07512 rev. *b page 5 of 19 table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write = 0 9 write = 0 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte from master ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read = 1 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop byte 0: control register 0 bit @pup name description 7 0 reserved, set= 0 6 1 pcif pci pci drive strength override 0 = force all pci and pcif outputs to low drive strength 1= force all pci and pcif outputs to high drive strength 5 0 reserved reserved, set= 0 4 hw fs_e power up latched value of fs_e pin 3 hw fs_d power up latched value of fs_d pin 2 hw fs_c power up latched value of fs_c pin 1 hw fs_b power up latched value of fs_b pin 0 hw fs_a power up latched value of fs_a pin byte 1: control register 1 bit @pup name description 7 0 reserved reserved, set = 0 6 1 reserved reserved, set = 1 5 1 reserved reserved, set = 1 4 1 reserved reserved, set = 1 3 1 reserved reserved, set = 1 2 1 cput_itp, cpuc_itp cput/c_itp output enable 0 = disabled (three-state), 1 = enabled 1 1 cput1, cpuc1 cpu(t/c)1 output enable, 0 = disabled (three-state), 1 = enabled 0 1 cput0, cpuc0 cpu(t/c)0 output enable 0 = disabled (three-state), 1 = enabled
CY28405 document #: 38-07512 rev. *b page 6 of 19 byte 2: control register 2 bit @pup name description 7 0 reserved reserved, set = 0 6 0 reserved reserved, set = 0 5 0 cput_itp, cpuc_itp cput/c_itp pwrdwn drive mode 0 = driven in power- down, 1 = three-state 4 0 cput1, cpuc1 cpu(t/c)1 pwrdwn drive mode 0 = driven in power-down, 1 = three-state 3 0 cput0, cpuc0 cpu(t/c)0 pwrdwn drive mode 0 = driven in power-down, 1 = three-state 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 3: control register 3 bit @pup name description 7 1 sw pci_stp function 0= pci_stp assert, 1= pci_stp deassert when this bit is set to 0, all stoppable pci and pcif outputs will be stopped in a synchronous manner with no short pulses. when this bit is set to 1, all st opped pci and pcif outputs will resume in a synchronous manner with no short pulses. 6 1 reserved reserved 5 1 pci5 pci5 output enable 0 = disabled, 1 = enabled 4 1 pci4 pci4 output enable 0 = disabled, 1 = enabled 3 1 pci3 pci3 output enable 0 = disabled, 1 = enabled 2 1 pci2 pci2 output enable 0 = disabled, 1 = enabled 1 1 pci1 pci1 output enable 0 = disabled, 1 = enabled 0 1 pci0 pci0 output enable 0 = disabled, 1 = enabled byte 4: control register 4 bit @pup name description 7 0 usb_48 usb 48 drive strength control 0 = high drive strength, 1 = low drive strength 6 1 usb_48 usb_48 output enable 0 = disabled, 1 = enabled 5 0 pcif2 allow control of pcif2 with assertion of sw pci_stp 0 = free running, 1 = stopped with sw pci_stp 4 0 pcif1 allow control of pcif1 with assertion of sw pci_stp 0 = free running, 1 = stopped with sw pci_stp 3 0 pcif0 allow control of pcif0 with assertion of sw pci_stp 0 = free running, 1 = stopped with sw pci_stp 2 1 pcif2 pcif2 output enable 0 = disabled, 1 = enabled 1 1 pcif1 pcif1 output enable 0 = disabled, 1 = enabled 0 1 pcif0 pcif0 output enable 0 = disabled, 1 = enabled
CY28405 document #: 38-07512 rev. *b page 7 of 19 byte 5: control register 5 bit @pup name description 7 1 dot_48 dot_48 output enable 0 = disabled, 1 = enabled 6 1 reserved reserved 5 hw 3v66_3/vch/selvch 3v66_3/vch/selvch frequency select 0 = 3v66 mode, 1 = vch (48mhz) mode may be written to override the power-up value. 4 1 3v66_3/vch/selvch 3v66_3/ vch/selvch output enable 0 = disabled,1 = enabled 3 1 reserved reserved 2 1 3v66_2 3v66_2 output enable 0 = disabled, 1 = enabled 1 1 3v66_1 3v66_1 output enable 0 = disabled, 1 = enabled 0 1 3v66_0 3v66_0 output enable 0 = disabled, 1 = enabled byte 6: control register 6 bit @pup name description 70ref pcif pci 3v66 3v66_3/vch/selvch usb_48 dot_48 cput, cput_itp cpuc,cpuc_itp test clock mode 0 = disabled, 1 = enabled when test clock mode is enabled, the fs_a/ref_0 pin reverts to a dedicated fs_a input, allowing asynchronous selection between hi-z and ref/n mode. 6 0 reserved reserved, set = 0 5 0 reserved reserved, set = 0 4 0 reserved reserved, set = 0 3 0 reserved reserved, set = 0 20pcif pci 3v66 cput,cput_itp cpuc,cpuc_itp spread spectrum enable 0 = spread off, 1 = spread on 1 1 ref_1 ref_1 output enable 0 = disabled, 1 = enabled 0 1 ref_0 ref_0 output enable 0 = disabled, 1 = enabled byte 7: vendor id bit @pup name description 7 0 revision code bit 3 6 1 revision code bit 2 5 0 revision code bit 1 4 0 revision code bit 0 3 1 vendor id bit 3 2 0 vendor id bit 2 1 0 vendor id bit 1 0 0 vendor id bit 0
CY28405 document #: 38-07512 rev. *b page 8 of 19 byte 8: control register 8 bit @pup name description 70cpu pcif pci 3v66 spread spectrum selection ?000? = 0.20% triangular ?001? = + 0.12, ? 0.62% ?010? = + 0.25, ? 0.75% ?011? = ?0.05, ? 0.45% triangular ?100? = 0.25% ?101? = + 0.00, ? 0.50% ?110? = 0.5% ?111? = 0.38% 61 51 4 0 fsel_4 sw frequency selection bits. see table 1 . 3 0 fsel_3 2 0 fsel_2 1 0 fsel_1 0 0 fsel_0 byte 9: control register 9 bit @pup name description 7 0 pcif pcif clock output drive strength control 0 = low drive strength, 1 = high drive strength 6 0 pci pci clock output drive strength 0 = low drive strength, 1 = high drive strength 5 0 3v66 3v66 clock output drive strength 0 = low drive strength, 1 = high drive strength 4 1 ref ref clock output drive strength 0 = low drive strength, 1 = high drive strength 3 1 reserved reserved 2 1 reserved reserved 1 0 reserved vendor test mode (always program to 0) 0 0 reserved vendor test mode (always program to 0) byte 10: control register 10 bit @pup name description 7 0 pci_skew1 pci skew control 00 = normal 01 = ?500 ps 10 = reserved 11 = +500 ps 6 0 pci_skew0 5 0 3v66_skew1 3v66 skew control 00 = normal 01 = ?150 ps 10 = +150 ps 11 = +300 ps 4 0 3v66_skew0 3 1 reserved reserved, set = 1 2 1 reserved reserved, set = 1 1 1 reserved reserved, set = 1 0 1 reserved reserved, set = 1
CY28405 document #: 38-07512 rev. *b page 9 of 19 byte 11: contro l register 11 bit @pup name description 7 0 reserved vendor test mode (always program to 0) 6 0 recovery_frequency this bit allows selection of the frequency setting that the clock will be restored to once the system is rebooted 0: use hardware settings 1: use last sw table programmed values 5 0 watchdog time stamp reload to enable this function the register bit must first be set to ?0? before toggling to ?1?. 0: do not reload 1: reset timer but continue to count. 4 0 wd_alarm this bit is set to ?1? when th e watchdog times out. it is reset to ?0? when the system clears the wd_timer time stamp 3 0 wd_timer3 watchdog timer time stamp selection: 0000: off 0001: 2 second 0010: 4 seconds 0011: 6 seconds . . . 1110: 28seconds 1111: 30seconds 2 0 wd_timer2 10wd_timer1 0 0 wd_timer0 byte 12: control register 12 bit @pup name description 7 0 cpu_fsel_n8 if prog_freq_en is set, the values programmed in cpu_fsel_n[8:0] and cpu_fsel_m[6:0] will be used to det ermine the cpu output frequency. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when it is clear ed, the same frequency ratio stated in the latched fs[e:a] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 6 0 cpu_fsel_n7 5 0 cpu_fsel_n6 4 0 cpu_fsel_n5 3 0 cpu_fsel_n4 2 0 cpu_fsel_n3 1 0 cpu_fsel_n2 0 0 cpu_fsel_n1 byte 13: control register 13 bit @pup name description 7 0 cpu_fsel_n0 if prog_freq_en is set, the values programmed in cpu_fsel_n[8:0] and cpu_fsel_m[6:0] will be used to det ermine the cpu output frequency. the setting of fs_override bit determines the frequency ratio for cpu and other output clocks. when it is cleared, the same frequency ratio stated in the latched fs[e:a] register will be used. when it is set, the frequency ratio stated in the sel[4:0] register will be used. 60cpu_fsel_m6 50cpu_fsel_m5 40cpu_fsel_m4 30cpu_fsel_m3 20cpu_fsel_m2 10cpu_fsel_m1 00cpu_fsel_m0 byte 14: control register 14 bit @pup name description 7 0 fs_(e:a) fs_override 0 = select operating frequency by fs(e:a) input pins 1 = select operating frequency by fsel(4:0) settings 6 1 reserved reserved, set = 1 5 0 reserved reserved, set = 0
CY28405 document #: 38-07512 rev. *b page 10 of 19 dial-a-frequency programming when the programmable output frequency feature is enabled (pro_freq_en bit is set), the cpu output frequency is deter- mined by the following equation: fcpu = g * n/m ?n? and ?m? are the values programmed in programmable frequency select n-value register and m-value register, respectively. ?g? stands for the pll gear constant, which is determined by the programmed value of fs[e:a] or sel[4:0]. the value is listed in ta ble 1 . the ratio of n and m need to be greater than ?1? [n/m> 1]. the following table lists set of n and m values for different frequency output ranges. this example use a fixed value for the m-value register and sele ct the cpu output frequency by changing the value of the n-value register. crystal recommendations the CY28405 requires a parallel resonance crystal . substituting a series resonance crystal will cause the CY28405 to operate at the wrong frequency and violate the ppm specification. for most a pplications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. crystal loading crystal loading plays a critical ro le in achieving low ppm perfor- mance. to realize low ppm perf ormance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (cl). figure 1 shows a typical crystal configuration using the two trim capacitors. an important clarification for the following discussion is that the trim capa citors are in series with the crystal not parallel. it?s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. this is not true . 4 0 reserved reserved, set = 0 3 0 reserved reserved, set = 0 2 0 reserved reserved, set = 0 1 0 reserved reserved, set = 0 0 0 pro_freq_en programmabl e output frequencies enabled 0 = disabled, 1 = enabled byte 14: control register 14 (continued) bit @pup name description table 5. examples of n and m value for different cpu frequency range frequency ranges gear constants fixed value for m-value register range of n-value register for different cpu frequency 100 ?125 24004009.32 48 200 ? 250 126 ? 166 32005345.76 48 189 ? 249 167 ? 200 48008018.65 48 167 ? 200 table 6. crystal recommendations frequency (fund) cut loading load cap drive (max.) shunt cap (max.) motional (max.) tolerance (max.) stability (max.) aging (max.) 14.31818 mhz at parallel 20 pf 0.1 mw 5 pf 0.016 pf 50 ppm 50 ppm 5 ppm
CY28405 document #: 38-07512 rev. *b page 11 of 19 calculating load capacitors in addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal load ing. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitive loading on both sides. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this mean the total capac- itance on each side of the cryst al must be twice the specified load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitative loading on both sides. use the following formulas to calculate the trim capacitor values for ce1 and ce2. cl ........................................... .........crystal load capacitance cle ......................................... actual loading seen by crystal .............. .............. .......... using standard va lue trim capacitors ce ..................................................... external trim capacitors cs ........................................... .. stray capacitance (trace,etc) ci ............. internal capacitance (lead frame, bond wires etc) pd# (power-down) clarification the pd# pin is used to shut off all clocks and plls without having to remove power from the device. all clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the power down state. pd# ? assertion when pd# is sampled low by two consecutive rising edges of the cpuc clock then all clo ck outputs (except cput) clocks must be held low on their next high to low transition. cpu clocks must be held with cput clock pin driven high with a value of 2x iref and cpuc undr iven as the default condition. there exists an i 2 c bit that allows for the cput/c outputs to be three-stated during power-down. due to the state of internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete figure 1. crystal capacitive clarification xtal ce2 ce1 cs1 cs2 x1 x2 ci1 ci2 clock chip trace 2.8pf trim 33pf pin 3 to 6p figure 2. crystal loading example load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl - (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 () 1 = cle pwrdwn# 3v66, 66mhz usb, 48mhz pci, 33mhz ref, 14.31818 cpuc, 133mhz cput, 133mhz figure 3. power-down assertion timing waveforms
CY28405 document #: 38-07512 rev. *b page 12 of 19 pd# deassertion the power-up latency between pd# rising to a valid logic ?1? level and the starting of all clocks is less than 1.8 ms. the cput/c outputs must be driven to greater than 200 mv is less than 300 s. ref, 14.31818 tdrive_pwrdn# <300 s, >200mv pwrdwn# cpuc, 133mhz cput, 133mhz 3v66, 66mhz usb, 48mhz pci, 33mhz tstable <1.8ms figure 4. power-down deassertion timing waveforms fs_a, fs_b vtt_pwrgd# pwrgd_vrm vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd# is ignored figure 5. vtt_pwrgd timing diagram
CY28405 document #: 38-07512 rev. *b page 13 of 19 vtt_pwrgd# = low delay >0.25ms s1 power off s0 vdda = 2.0v sample inputs straps s2 normal operation wait for 1.146ms enable outputs s3 vtt_pwrgd# = toggle vdda = off figure 6. clock generator power-up/run state diagram
CY28405 document #: 38-07512 rev. *b page 14 of 19 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dda analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 +150 c t a temperature, operating ambient functional 0 70 c t j temperature, junc tion functional ? 150 c esd hbm esd protection (human body model ) mil-std-883, method 3015 2000 ? v ? jc dissipation, junction to case mil-spec 883e method 1012.1 15 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 45 c/w ul?94 flammability rating at 1/8 in. v ? 0 msl moisture sensitivity level 1 multiple supplies : the voltage on any input or i/o pin cannot exceed th e power pin during power-up. power supply sequencing is not required. dc electrical specifications parameter description conditions min. max. unit v dd , v dda 3.3 operating voltage 3.3v 5% 3.135 3.465 v v ili2c input low voltage sdata, sclk ? ? 1.0 v ihi2c input high voltage sdata, sclk 2.2 ? ? v il input low voltage v ss ? 0.5 0.8 v v ih input high voltage 2.0 v dd + 0.5 v i il input leakage current except pull-ups or pull-downs 0 < v in < v dd ?5 5 a v ol output low voltage i ol = 1 ma ? 0.4 v v oh output high voltage i oh = ?1 ma 2.4 ? v i oz high-impedance output current ?10 10 a c in input pin capacitance 2 5 pf c out output pin capacitance 3 6 pf l in pin inductance ? 7 nh v xih xin high voltage 0.7v dd v dd v v xil xin low voltage 0 0.3v dd v i dd dynamic supply current at 200 mhz and all outputs loaded per table 9 and figure 7 ? 280 ma i pd power-down supply current pd# asserted ? 1 ma
CY28405 document #: 38-07512 rev. *b page 15 of 19 ac electrical specifications parameter description conditions min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is driven from an external clock source 69.841 71.0 ns t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ?10.0ns t ccj xin cycle to cycle jitter as an average over 1 s duration ?500ps l acc long-term accuracy over 150ms 300 ppm cpu at 0.7v t dc cput and cpuc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz cput and cpuc period measured at crossing point v ox 9.9970 10.003 ns t period 133-mhz cput and cpuc period measured at crossing point v ox 7.4978 7.5023 ns t period 200-mhz cput and cpuc period measured at crossing point v ox 4.9985 5.0015 ns t skew any cpu to cpu clock skew measured at crossing point v ox ?100ps t ccj cpu cycle to cycle jitter measured at crossing point v ox ?125ps t r / t f cput and cpuc rise and fall times measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/ (t r + t f ) ?20% ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math average, see figure 7 660 850 mv v low voltage low math average,see figure 7 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high +0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 7 . measure se ? 0.2 v 3v66 t dc 3v66 duty cycle measurement at 1.5v 45 55 % t period spread disabled 3v66 period measur ement at 1.5v 14.9955 15.0045 ns t period spread enabled 3v66 period measur ement at 1.5v 14.9955 15.0799 ns t high 3v66 high time measuremen t at 2.4v 4.9500 ? ns t low 3v66 low time measuremen t at 0.4v 4.5500 ? ns t r / t f 3v66 rise and fall times measured between 0.4v and 2.4v 0.5 2.0 ns t skew any 3v66 to any 3v66 clock skew measurement at 1.5v ? 250 ps t ccj 3v66 cycle to cycle jitter measurement at 1.5v ? 250 ps pci/pcif t dc pcif and pci duty cycle measurement at 1.5v 45 55 % t period spread disabled pcif/pci period m easurement at 1. 5v 29.9910 30.0009 ns t period spread enabled pcif/pci period m easurement at 1. 5v 29.9910 30.1598 ns t high pcif and pci high time measurement at 2.4v 12.0 ? ns
CY28405 document #: 38-07512 rev. *b page 16 of 19 t low pcif and pci low time measurement at 0.4v 12.0 ? ns t r / t f pcif and pci rise and fall times measured between 0.4v and 2.4v 0.5 2.0 ns t skew any pci clock to any pci clock skew measurement at 1.5v ? 500 ps t ccj pcif and pci cycle to cycle jitter measurement at 1.5v ? 250 ps dot t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 20.8257 20.8340 ns t high dot high time measuremen t at 2.4v 8.994 10.486 ns t low dot low time measuremen t at 0.4v 8.794 10.386 ns t r / t f rise and fall times measured between 0.4v and 2.4v 0.5 1.0 ns t ccj cycle to cycle jitter 10- s period ? 350 ps usb t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 20.8257 20.8340 ns t high usb high time measuremen t at 2.4v 8.094 10.036 ns t low usb low time measuremen t at 0.4v 7.694 9.836 ns t r / t f rise and fall times measured between 0.4v and 2.4v 1.0 2.0 ns t ccj cycle to cycle jitter 125- s period ? 350 ps ref t dc ref duty cycle measurement at 1.5v 45 55 % t period ref period measurement at 1.5v 69.827 69.855 ns t r / t f ref rise and fall times measured between 0.4v and 2.4v 1.0 4.0 v/ns t ccj ref cycle to cycle jitter measurement at 1.5v ? 1000 ps enable/disable and set-up t stable all clock stabilization from power-up ? 1.5 ms t ss stopclock set-up time 10.0 ? ns t sh stopclock hold time 0 ? ns table 7. group timing relationship and tolerances group conditions offset min. max. 3v66 to pci 3v66 leads pci 1.5 ns 3.5 ns table 8. usb to dot phase offset parameter typical value tolerance dot skew 0 0.0 ns 1000 ps usb skew 180 0.0 ns 1000 ps vch skew 0 0.0 ns 1000 ps ac electrical specifications (continued) parameter description conditions min. max. unit
CY28405 document #: 38-07512 rev. *b page 17 of 19 test and measurement set-up for differential cpu an d src output signals the following diagram shows lumped test load configurations for the differential host clock outputs. table 9. maximum lumped capacitive output loads clock max load units pci clocks 30 pf 3v66 clocks 30 pf usb clock 20 pf dot clock 10 pf ref clock 30 pf table 10.cpu clock current select function board target trace/term z reference r, i ref ? v dd (3*r ref ) output current v oh @ z 50 ohms r ref = 475 1%, i ref = 2.32 ma i oh = 6*i ref 0.7v @ 50 ordering information part number package type product flow CY28405oc 48-pin shrunk small outline package (ssop) commercial, 0 to 70 c CY28405oct 48-pin shrunk small outline package (ssop) ? tape and reel commercial, 0 to 70 c lead free CY28405oxc 48-pin shrunk small outline package (ssop) commercial, 0 to 70 c CY28405oxct 48-pin shrunk small outline package (ssop) ? tape and reel commercial, 0 to 70 c cput t pcb t pcb cpuc 33? 33? 49.9? 49.9? measurement point 2pf 475? iref measurement point 2pf figure 7. 0.7v load configuration 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals td c probe output under test load cap - - figure 8. lumped load for single-ended output signals (for ac parameter measurement)
CY28405 document #: 38-07512 rev. *b page 18 of 19 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimensions purchase of i 2 c components from cypress, or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided t hat the system conforms to the i 2 c standard specification as defined by philips. intel and pentium are registered tr ademarks of intel corporation. dial-a-frequency is a registered trademark of cypress semiconductor. all product and company names mentioned in this docum ent are trademarks of their respective holders. 48-leadshrunksmalloutlinepackageo48 51-85061-*c
CY28405 document #: 38-07512 rev. *b page 19 of 19 document history page document title: CY28405 ck409-compliant clock synthesizer document number: 38-07512 rev. ecn no. issue date orig. of change description of change ** 125354 04/15/03 rgl new data sheet *a 127159 06/16/03 rgl removed src functionality modified the title to ck409-compliant clock synthesizer *b 235894 see ecn rgl removed all items referencing to 166mhz added lead free devices in the ordering information table

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